As the artificial intelligence (AI) revolution drives data centers to expand from isolated server racks to massive, interconnected clusters of thousands of accelerators, a fundamental physics problem has emerged: copper, the traditional lifeblood of electrical signaling, is running out of headroom. To maintain the blistering pace of AI model training and inference, data movement must become as efficient as the compute itself. The industry’s solution—silicon photonics—is moving from a long-promised research curiosity to an industrial necessity.
Leading the charge in this transition is STMicroelectronics (ST), which is betting that the next phase of the optical interconnect market will be defined not by scientific breakthroughs, but by the rigorous demands of industrialization: volume production, compact packaging, and long-term reliability.
The Limits of Copper: Why Optics are Essential
For decades, copper-based electrical links have served the industry well. However, as bandwidth demands hit the terabit-per-second threshold, copper is encountering severe physical constraints regarding reach, power consumption, and signal integrity.
In modern AI data centers, the demand for routing capability and bandwidth within the rack is skyrocketing. Copper cabling is becoming a liability, consuming too much power and struggling to maintain signal fidelity over the distances required by increasingly dense AI clusters. Optical links offer a superior alternative, providing longer reach, significantly lower signal loss, and the potential for much more compact "optical engines" that convert electrical data to light and back again.
According to Sylvie Gellida, general manager of ST’s Optical and RF Foundry Division, the industry is at a crossroads. "AI data centers need more routing capability in the rack and more bandwidth in less physical space," she explained. "Copper increasingly constrains both."
A Chronology of a Market Maturation
STMicroelectronics’ entry into this space is a case study in technological patience. The company’s involvement with silicon photonics spans a decade, beginning with its earlier PIC25 platform, which supported 25-GBaud signaling for 50G-per-lane applications.
While that technology successfully reached production, it arrived ahead of its time. "The killer application wasn’t there," Gellida noted. "ST put the business activity on hold, but not the R&D, because we believed the application would eventually come."
That "killer application" is the modern AI factory. With the explosion of generative AI and Large Language Models (LLMs), the demand for high-speed, low-latency interconnects has finally caught up with the technology. "All the planets are now aligned," Gellida said. "We’re on time to address this market."
Industrializing the PIC100 Platform
ST’s current flagship, the PIC100 platform, is designed for the 100-GBaud signaling era, enabling 200G-per-lane applications. What sets ST apart in a crowded field of photonics players is its manufacturing strategy: shifting the production of photonic integrated circuits (PICs) onto 300-mm wafers.
By utilizing standard 300-mm semiconductor manufacturing lines—the same infrastructure used for high-volume CMOS logic—ST is achieving yields and reliability metrics that are fundamentally different from the 200-mm or niche production lines that have historically dominated the photonics space.
"Today we’re supplying silicon photonics wafers in Crolles, France, on 300-mm wafers," Gellida stated. "For the volumes required by AI data centers and AI factories, 300-mm manufacturing brings together the tools, accuracy, volume, and yield necessary to scale."
The "One-Stop Shop" Strategy
ST is positioning itself as more than just a wafer foundry. The company is effectively building an ecosystem. By combining its silicon photonics platform with its established BiCMOS expertise for laser drivers and electronic ICs, and integrating STM32 microcontrollers for module management, ST is attempting to become a "one-stop shop" for optical interconnect components.
This strategy includes advanced packaging capabilities such as through-silicon vias (TSVs), bumping, and rigorous testing support. By providing these building blocks, ST is lowering the barrier to entry for transceiver module makers and design houses, allowing them to focus on the end-product architecture rather than the underlying material science.
Proof Point: The Sicoya 1.6T Collaboration
The viability of this platform approach was demonstrated recently by Sicoya, a Berlin-based silicon photonics specialist. At the Optical Fiber Communication (OFC) conference, Sicoya unveiled a PIC100-based OSFP module targeting 1.6T DR8 operation—a configuration that utilizes eight lanes running at 200G each.
Hanjo Rhee, CTO and managing director at Sicoya, emphasizes that the significance of this demo is both technical and industrial. By using ST’s PIC100 and associated electronic ICs, Sicoya was able to employ a "die-stacking" architecture. In this design, the transimpedance amplifier (TIA) is stacked directly on top of the photonic integrated circuit.
"The demo proved that these more complex photonic products for these pluggables are possible and that they are possible with ST’s platform," Rhee told EE Times.
The die-stacking approach provides several critical advantages:
- Shortened RF Paths: By placing the TIA directly on the PIC, the distance between the photodiode and the electronic amplifier is minimized, drastically reducing parasitics and improving signal integrity.
- Integrated Control Loops: Complex features, such as variable optical attenuators, can be managed internally between the EIC and PIC, offloading the need for external microcontroller intervention.
- Foundry Scalability: Unlike monolithic integration—where electronics and photonics share the same substrate—die stacking allows both domains to be optimized independently, leading to faster development cycles and easier manufacturing scaling.
Implications for the Future: NPO and CPO
As the industry looks beyond pluggable transceivers toward Near-Packaged Optics (NPO) and, eventually, Co-Packaged Optics (CPO), the challenges of industrialization will only intensify.
Moving optical engines closer to the ASIC—or even onto the same substrate as the GPU—promises to eliminate the need for power-hungry digital signal processors (DSPs) by reducing the need for retiming. However, this creates a formidable set of new hurdles: thermal management, complex fiber-attachment techniques, and entirely new serviceability models for data center operators.
Rhee points out that standard reflow soldering, used in conventional PCB manufacturing, is not yet compatible with optical connectors. "You can do this in smaller volumes for sure," Rhee said, "but to do this at large scale is very hard."
The industry is currently grappling with how to build detachable optical connectors that can survive the high-heat environments of modern server board manufacturing. Large packaging houses are now racing to solve these assembly puzzles.
Conclusion: The Era of Industrial Photonics
The AI data center of 2026 and beyond will be defined by the density of its interconnects. While researchers have spent years perfecting the light-manipulation capabilities of silicon photonics, the current battle is being fought in the cleanrooms and on the assembly lines.
The transition from pluggable transceivers to fully integrated, co-packaged optical systems is not just a technological shift; it is an industrial evolution. Companies like STMicroelectronics, by leveraging the economies of scale inherent in 300-mm wafer manufacturing, and partners like Sicoya, by innovating in packaging and die-stacking, are proving that silicon photonics is finally ready for the prime time.
The "killer application" is here, and the race to industrialize the optical backbone of the AI era has officially begun. The companies that can marry high-performance photonic design with the unforgiving demands of high-volume, high-reliability manufacturing will be the ones that define the infrastructure of the next decade.
