In the first two installments of this series, we mapped the Design Automation Conference (DAC) 2026 exhibit floor as a complex, multi-layered AI ecosystem—from the foundational compute engines to the agentic flows that now redefine EDA (Electronic Design Automation). We established that the industry is in the midst of a fundamental shift where users are no longer just consumers of vendor tools but active architects of their own AI-driven design methodologies.
However, the most critical question remains: What does it actually take to build the silicon that powers this revolution? As the industry pivots from the "AI for chip design" narrative to the reality of designing AI-specific silicon, the focus shifts to the physical, thermal, and architectural constraints of accelerators, memory systems, and advanced interconnects.
Amid the cacophony of funding announcements and market hype, DAC 2026 serves as the definitive reality check. The agents and design flows are merely the means; the silicon is the point.
The Demand Side: Setting the Requirements for AI Silicon
To understand the engineering hurdles, one must first look at the architects of the modern data center. At DAC 2026, the demand side is speaking directly to the supply side. Qualcomm EVP and CTO Baaziz Achour will open the plenary sessions with "Design Automation for Emerging AI: From AI Chips to Data Center," setting the tone for a conference obsessed with scale.
Nvidia’s Timothy Costa will further define the landscape in his Sunday evening SKYTalk, focusing on the intersection of AI supercomputing and EDA. Perhaps most significant for working engineers is the Wednesday morning session by Artour Levin, VP of AI Silicon Engineering at Microsoft. Levin’s abstract serves as a de facto requirements document for the industry: as accelerators scale from individual chips to massive, rack-level systems, the "hard problems" are no longer contained within traditional silos. They exist at the boundaries—where compute, memory, and interconnects meet software.
Levin’s thesis aligns with a core industry sentiment: traditional EDA methodologies were built for a modular, siloed world. The current generation of AI accelerators, however, demands a holistic rethink. When a chip’s performance is defined by its ability to manage data flow across hundreds of die, the boundaries between logic, memory, and thermal management become the primary failure points.
Chronology of Innovation: The Engineering Track
The heart of DAC 2026 beats in the Engineering Track—a peer-reviewed, marketing-free zone where practitioners present their triumphs and failures. With 15 sessions and nearly 90 presentations, this track is the guided tour for those making AI hardware a reality.
The Recursive Loop: AI Designing AI
On Tuesday, the session "AI-Accelerated IP Libraries: From Optimization to Signoff" will address the recursion currently defining the industry. Engineers are now using AI to design the very standard cells and IP blocks that constitute AI chips.
Current research highlights include:
- Tailor-made Cell Variants: Moving beyond the industry-standard ~30 variants per gate type, AI-driven transistor-level sizing is generating millions of cell variants, yielding double-digit power and timing improvements.
- Automated Specification Engineering: New ML-driven flows are parsing complex hard-IP integration documents, saving weeks of manual labor and eliminating human error in requirements tracking.
- Unified QA Frameworks: Intel’s presentation on using Siemens’ Solido Crosscheck for automated Liberty model validation across 1,000+ cells and 30+ PVT (Process, Voltage, Temperature) corners highlights the necessity of "trust but verify" in AI-augmented design.
The Physics of Power and Heat
Physics does not negotiate, particularly when dealing with the power densities of modern AI accelerators. The session "A Good Grid Can Never be IR-Responsible" tackles the brutal reality of power delivery.
Key takeaways from the engineering front lines include:
- Hierarchical EMIR Analysis: For reticle-scale SoCs, flat analysis is no longer viable. New hierarchical approaches are achieving 10× runtime reductions while maintaining signoff-level accuracy.
- Multi-die Reality Checks: Analysis of 12-high HBM (High Bandwidth Memory) stacks has revealed a staggering 442% increase in maximum IR drop compared to single-die analysis. This finding effectively kills the long-held notion that multi-die systems can be signed off die-by-die.
- Thermal Mitigation: A collaboration between Broadcom and Synopsys demonstrates early thermal analysis for face-to-face 3DIC stacking that correlates to within 3°C of post-silicon reality—a crucial breakthrough for high-density AI chiplets.
Supporting Data: Managing the "Memory Wall"
The memory wall remains the defining constraint of the AI era. Throughout the conference, the emphasis shifts from raw compute to the efficient movement of data.
In the "IP Design for Mixed-Signal and High-Speed SoCs" session, engineers will detail a formal verification approach that successfully identified a deeply buried credit-management bug in PCIe Gen6/7 logic. As bandwidth requirements explode, these interfaces have become the most vulnerable points in the architecture. Furthermore, the push for agentic AI at the edge is driving innovations like custom NPUs (Neural Processing Units) that deliver 100 GMAC/s in under 200,000 gates—a testament to the extreme efficiency possible when the ISA (Instruction Set Architecture) is perfectly tuned to the application.
Official Perspectives: The Holistic Rethink
Simon Davidmann, a leading voice in the EDA space, has long argued that the most interesting question is not whether AI helps chip design, but whether it forces a holistic rethink of our tools. This sentiment is echoed across the DAC Pavilion, particularly in the "Gladiator" sessions and the "AI and Multi-die: A Reinforcing Cycle" special session.
The prevailing industry consensus is that AI workloads are the "stress test" for every EDA silo. Because an AI accelerator requires a perfect synchronization of logic, memory, interconnect, power, and thermal management, it forces companies to break down their organizational and technical silos. This is not merely an optimization; it is a fundamental shift in how we verify complex systems.
Implications for the Future of Silicon
As we look toward the conclusion of DAC 2026, the implications for the semiconductor industry are profound:
- The End of Siloed Design: The "AI-assisted" design paradigm is moving from novelty to necessity. Companies that continue to operate with isolated teams for logic, power, and physical design will likely face significant delays and yield issues as complexity scales.
- The Rise of Specification Engineering: With AI now handling the mundane aspects of signoff and optimization, the human element of engineering is shifting toward high-level architectural definition and rigorous, AI-assisted verification.
- The Multi-Die Mandate: The industry has crossed the Rubicon into the multi-die era. Whether it is 3DIC, chiplets, or advanced packaging, the ability to manage thermal and power integrity across disparate dies is now the primary competitive differentiator.
- Lifecycle Management: The focus is moving beyond the initial tapeout. Silicon lifecycle management, using embedded trace and AI-driven inference engines to hunt for silent data corruption in the field, is becoming a standard practice for mission-critical AI hardware.
Conclusion: The Road Forward
Creating AI chips is the ultimate engineering challenge of our time. It requires a synthesis of ancient physical laws and cutting-edge algorithmic optimization. For those attending DAC 2026 in Long Beach, the Engineering Track provides more than just a schedule; it provides a roadmap for the future of hardware.
Whether you are looking at the recursive power of AI-designed IP, the complex thermal challenges of 3D stacking, or the desperate need to break down the silos that impede performance, the message of this year’s conference is clear: The tools are changing, the workflows are evolving, and the silicon is becoming more capable—and more difficult to build—than ever before.
As we bridge the gap between the "map" provided in Part 1 and the "user-defined flows" explored in Part 2, this final installment serves as the anchor. The Engineering Track is where the rubber meets the road. It is where the practitioners—the people who actually sign off the chips that power the world’s AI models—share the truth about what works, what breaks, and what comes next. See you in Long Beach.
Frank Schirrmeister writes about semiconductors, EDA, and system design. He serves as program chair of the DAC Engineering Track; this series is written in that capacity, not on behalf of his employer, Synopsys. Opinions are his own.
